Short Time Decision VLSI Fuzzy Processor
نویسندگان
چکیده
This paper mainly describes the architecture of a very small size high speed fuzzy chip with two inputs and one output. In particular, an input data set rate of 80 ns is obtained by means of 4 clock pipeline cycles synchronized with a 50 MHz signal. In addition the chip architecture processes only the actives rules by a parallel-pipeline structure. The design has been done using VHDL language as front-end tool and CAD layout utilities as back-end ones. Moreover, by means of cell-based digital 0.7 μ m CMOS ES2 technology library, the VHDL synthesis and layout design has produced a chip area of about 10 square mm.
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